1. Field of the Invention
The present invention relates to programmable devices and, more particularly, to a memory element containing a plurality of such programmable devices and a logic circuit containing such programmable devices.
2. Description of Related Art
Memory and logic devices such as complementary metal-oxide-semiconductor (CMOS) are major classes of integrated circuits. They are used in processor and memory chips such as microprocessors, microcontrollers, solid-state stand-alone and embedded memory circuits and other digital logic circuits.
The most widely used memory technologies are DRAM, SRAM, Floating gate (Flash), and MRAM. These existing technologies can not be integrated with high areal density and provide at the same time non-volatile and fast operation. In particular, Flash is too slow for many embedded applications, SRAM and DRAM loose their memory state when disconnected from a power supply, and SRAM and MRAM can only be manufactured with a limited areal density. In addition, the high programming voltage of Flash complicates integration with CMOS circuitry.
The logic state of CMOS is volatile and the input voltage has to be maintained. Always maintaining the input voltage will lead to considerable power consumption and heating in future CMOS generations.
WO 2007/110950 proposes the use of ferromagnetic multiferroic materials for building memory devices. However, such devices suffer from disadvantages. For example, currently no multiferroics are known that possess ferroelectric and ferromagnetic ordering at room temperature. Further, such devices would not be suited for significant miniaturization because below a certain size the superparamagnetic limit is reached. The term “superparamagnetic limit” is the size at which the magnetic anisotropy of a magnetic layer in a cell becomes comparable to kT, where k is Boltzmann's constant and T is the absolute temperature. The magnetization becomes unstable below that limit.